OSIRIS quantitative objectives have been based on initial thermal simulations for the two targeted applications:

I. Microwave applications

  • Potential cost of processed wafer: decrease of 30%
  • Thermal resistance improvement: 5°C.mm/W for 20 mm total gate development
  • Lifetime: improvement by around 1 order of magnitude (i.e. 10-20°C junction temperature decrease
    at given power dissipation)
  • Microwave gain: increase of 1dB
  • Electrical efficiency: increase of about 5% for high frequency CW applications (i.e. above 18 GHz)

II. Power electronics applications

  • Planar device: Thermal resistance improvement of 5°C.mm/W for 100 mm gate width.
  • Vertical device: to be determined.

It is forecast that by the end of this collaboration the TRL progress will be shifted from 3 to 5

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